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| STM1403 3 V FIPS-140 security supervisor with battery switchover Features STM1403 supports FIPS-140 security level 3+ - Four high-impedance physical tamper inputs - Over/under operating voltage detector - Security alarm (SAL) on tamper detection Supervisory functions - Automatic battery switchover - RST output (open drain) - Manual (push-button) reset input (MR) - Power-fail comparator (PFI/PFO) Vccsw (VCC switch output) - Low when switched to VCC - High when switched to VBAT (BATT ON indicator) Battery low voltage detector (power-up) Optional VREF (1.237 V) - (Available for STM1403A only) Low battery supply current (2.8 A, typ) Secure low profile 16-pin, 3 x 3 mm, QFN package QFN16, 3 mm x 3 mm (Q) Table 1. Device STM1403A Device summary Standard supervisory functions(1) Physical tamper inputs Over/under voltage alarms VREF (1.237 V) option Note(4) Note(4) VOUT status, during alarm ON High-Z Ground Vccsw status, during alarm Normal mode(2) High High STM1403B(3) STM1403C 1. Reset output, power-fail comparator, battery low detection (SAL, RST, PFO, and BLD are open drain). 2. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to battery. 3. Contact local ST sales office for availability. 4. Pin 9 is the VREF pin for STM1403A. It is the VTPU pin for STM1403B/C. August 2008 Rev 5 1/35 www.st.com 1 Contents STM1403 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 VOUT pin modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 1.1.2 1.1.3 STM1403A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM1403B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM1403C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 SAL, security alarm output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.1.9 2.1.10 2.1.11 2.1.12 2.1.13 2.1.14 TP1, TP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TP2, TP4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Vccsw, VCC switch output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 BLD, VBAT low voltage detect output (open drain) . . . . . . . . . . . . . . . . . 12 Active-low RST output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MR, manual reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PFO, power-fail output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PFI, power-fail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VREF, reference voltage output (1.237, typ) . . . . . . . . . . . . . . . . . . . . . . 12 VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VTPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 3.2 3.3 3.4 3.5 3.6 Reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Negative-going VCC transients and undershoot . . . . . . . . . . . . . . . . . . . . 16 4 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/35 STM1403 Contents 4.2 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 6 7 8 9 10 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3/35 List of tables STM1403 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating and AC measurement condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Physical and environmental tamper detection levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mechanical data . . . 31 Ordering information scheme (see Figure 30 on page 33 for marking information) . . . . . . 32 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4/35 STM1403 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 QFN16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Tamper pin (TP1 or TP3) normally high (NH) external hookup (switch closed) . . . . . . . . . . 9 Tamper pin (TP1 or TP3) normally high (NH) external hookup (switch open). . . . . . . . . . . 10 Tamper pin (TP2 or TP4) normally low (NL) external hookup (switch closed) . . . . . . . . . . 10 Tamper pin (TP2 or TP4) normally low (NL) external hookup (switch open). . . . . . . . . . . . 10 Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VBAT -to-VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VCC to reset propagation delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM1403 switchover diagram, condition A (VBAT < VSW) . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM1403 switchover diagram, condition B (VBAT > VSW) . . . . . . . . . . . . . . . . . . . . . . . . . 25 QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline . . . . . . . . . . . 30 QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint . . . . . . 31 Topside marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5/35 Description STM1403 1 Description The STM1403 family of security supervisors are a low power family of intrusion (tamper) detection chips targeted at manufacturers of POS terminals and other systems, to enable them to meet physical and/or environmental intrusion monitoring requirements as mandated by various standards, such as Federal Information Processing Standards (FIPS) Pub 140 entitled "Security Requirements for Cryptographic Modules," published by the National Institute of Standards and Technology, U.S. Department of Commerce), EMVCo, ISO, ZKA, and VISA PED. STM1403 supports target levels 3 and lower. The STM1403 includes automatic battery switchover, RST output (open drain), manual (push-button) reset input (MR), power-fail comparator (PFI/PFO), physical and/or environmental tamper detect/security alarm, and battery low voltage detect features. The STM1403A also offers a VREF (1.237 V) as an option on pin 9. On the STM1403B/C, this pin is VTPU (internally switched VCC or VBAT). 1.1 VOUT pin modes The STM1403 is available in three versions, corresponding to three modes of the VOUT pin (supply voltage out), when the SAL (security alarm) is asserted (active-low) upon tamper detection: 1.1.1 STM1403A VOUT stays ON (at VCC or VBAT) when SAL is driven low (activated). 1.1.2 STM1403B VOUT is set to High-Z when SAL is driven low (activated). 1.1.3 STM1403C VOUT is driven to ground when SAL is activated (may be used when VOUT is connected directly to the VCC pin of the external SRAM that holds the cryptographic codes). All variants (see Table 1: Device summary) are pin-compatible and available in a securityfriendly, low profile, 16-pin QFN package. 6/35 STM1403 Figure 1. Logic diagram Description VREF BLD(3) or VBAT VCC VTPU(1) VCCSW(2) MR STM1403 PFI TP1 (NH) VOUT RST(3) PFO(3) SAL(3) TP2 TP3 (NL) (NH) TP4 VSS (NL) AI09682 1. VREF only for STM1403A; VTPU for STM1403B/C. 2. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to battery. 3. SAL, RST, PFO, and BLD are open drain. Table 2. Vccsw(1) MR PFI TP1 - TP4 VOUT RST SAL (2) Signal names VCC switch output Manual (push-button) reset input Power-fail Input Independent physical tamper detect pins 1 through 4 Supply voltage output Active-low reset output Power-fail output Security alarm output Battery low voltage detect 1.237 V reference voltage Tamper pull-up (VCC or VBAT) Backup supply voltage Supply voltage Ground PFO(2) (2) BLD(2) VREF VTPU VBAT VCC VSS (3) (3) 1. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to battery. 2. SAL, RST, PFO, and BLD are open drain. 3. VREF only for STM1403A; VTPU for STM1403B/C. Note: See Section 2: Pin descriptions on page 11 for details. 7/35 Description Figure 2. QFN16 connections BLD(2) PFI VCCSW(1) VCC 16 1 2 3 4 5 6 7 15 14 13 12 11 10 8 9 STM1403 RST(2) MR SAL(2) VSS VOUT VBAT PFO(2) VREF or VTPU(3) TP1 TP2 TP3 (NH) (NL) (NH) TP4 (NL) AI09683 Note: See Section 2: Pin descriptions on page 11 for details. 1. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to battery. 2. SAL, RST, PFO, and BLD are open drain. 3. VREF only for STM1403A; VTPU for STM1403B/C Figure 3. VCC Block diagram VOUT BAT54J(1,2) VBAT(1) VINT MR PFI VPFI COMPARE VSO COMPARE VCCSW VRST COMPARE trec Generator RST(3) PFO(3) VDET COMPARE @ POWER-UP BLD(3) VTPU(4) 1.237V VREF Generator VREF(4) VHV COMPARE VLV TP1 (NH) TP2 (NL) TP3 (NH) TP4 (NL) COMPARE SAL(3) AI09684 1. BAT54J (from STMicroelectronics) recommended 2. Required for battery-reverse charging protection 3. Open drain 4. VREF only for STM1403; VTPU for STM1403B/C 8/35 STM1403 Figure 4. Hardware hookup Description Regulator Unregulated Voltage VIN VCC VCCSW VCC (1) VCC VCC VOUT 0.1F STM1403 C (2) LPSRAM R1 PFI R2 Push-Button BAT54J(4) VBAT 1.0F BLD(3) To Microprocessor MR RST(3) To Microprocessor Reset PFO(3) To Microprocessor NMI TP1 From Actuator Device (e.g., Switches, Wire Mesh) TP2 TP3 TP4 VREF(5) or VTPU To ADC To Physical Tamper Pins TPX AI09690 SAL(3) 1. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to battery. 2. Capacitor (C) is typically 10 F. 3. Open drain 4. Diode is required for battery reverse charge protection. 5. VREF only for STM1403; VTPU for STM1403B/C. Figure 5. Tamper pin (TP1 or TP3) normally high (NH) external hookup (switch closed) VOUT (STM1403A) or VTPU (STM1403B/C) Switch Normally Closed; Tamper Detection on Open TP1 or TP3 R(1) AI09698 1. R typical is 10 M. Resistors must be protected against conductive materials. 9/35 Description Figure 6. STM1403 Tamper pin (TP1 or TP3) normally high (NH) external hookup (switch open) VOUT (STM1403A) or VTPU (STM1403B/C) (1) R TP1 or TP3 Switch Normally Open Tamper Detection when Closed AI10461 1. R typical is 10M. Resistors must be protected against conductive materials. Figure 7. Tamper pin (TP2 or TP4) normally low (NL) external hookup (switch closed) VOUT (STM1403A) or VTPU (STM1403B/C) R(1) TP2 or TP4 Switch Normally Closed; Tamper Detection on Open AI09699 1. R typical is 10 M. Resistors must be protected against conductive materials. Figure 8. Tamper pin (TP2 or TP4) normally low (NL) external hookup (switch open) VOUT (STM1403A) or VTPU (STM1403B/C) Switch Normally Open; Tamper Detection when Closed TP2 or TP4 R(1) AI10462 1. R typical is 10 M. Resistors must be protected against conductive materials. 10/35 STM1403 Pin descriptions 2 Pin descriptions See Figure 1: Logic diagram and Table 2: Signal names for a brief overview of the signals connected to this device. 2.1 SAL, security alarm output (open drain) This signal can be generated when ANY of the following conditions occur: VINT > VHV, where VHV = upper voltage trip limit (4.2 V typ); and where VINT = VCC or VBAT; VINT < VLV, where VLV = lower voltage trip limit (2.0 V typ); and where VINT = VCC or VBAT; or When any of the physical tamper inputs, TP1 to TP4, change from their normal states to the opposite (i.e., intrusion of a physical enclosure). Note: 1 2 The default state of the SAL output during initial power-up is undetermined. The alarm function will operate either with VCC on or when the part is internally switched from VCC to VBAT. 2.1.1 TP1, TP3 Physical tamper detect pin set normally to high (NH). They are connected externally through a closed switch or a high-impedance resistor to VOUT (in the case of STM1403A) or VTPU (in the case of STM1403B/C. A tamper condition will be detected when the input pin is pulled low (see Figure 5 and Figure 6). If not used, tie the pin to VOUT (for STM1403A) or VTPU (for STM1403B/C). 2.1.2 TP2, TP4 Physical tamper detect pin set normally to low (NL). They are connected externally through a high-impedance resistor or a closed switch to VSS. A tamper condition will be detected when the input pin is pulled high (see Figure 7 and Figure 8). If not used, tie the pin to VSS. 2.1.3 Vccsw, VCC switch output This output is low when VOUT (see Section 2.1.10: VOUT on page 13) is internally switched to VCC; in this mode it may be used to turn on an external p-channel MOSFET switch which can source an external device directly from VCC for currents greater than 80 mA (bypassing the STM1403). This pin goes high when VOUT is internally switched to VBAT and may be used as a "BATT ON" indicator. If a security alarm (SAL) is issued on tamper, then the state of the Vccsw pin is as follows: 11/35 Pin descriptions 1. 2. 3. STM1403 STM1403A (VOUT remains ON when SAL is active-low): Vccsw pin will continue to operate in normal mode; STM1403B (VOUT is taken to High-Z when SAL is active-low): Vccsw pin will be set to high when this occurs; and STM1403C (VOUT is driven to ground when SAL is active-low): Vccsw pin will be set to high when this occurs. 2.1.4 BLD, VBAT low voltage detect output (open drain) This is an internally loaded test of the battery, activated only during a power-up sequence to insure that the battery is good either prior to or after encapsulation of the module. There are three customer options for VDET: 2.3 V (2.5 V - external diode drop of about 0.2 V) for a 3 V lithium cell 2.5 V (2.7 V - 0.2 V) for a 3 V lithium cell or 3.2 V (3.4 V - 0.2 V) for a 3.68 V lithium "AA" battery This output pin will go active-low when it detects a voltage on the VBAT pin below VDET. BLD will be released when VCC drops below VRST. 2.1.5 Active-low RST output (open drain) Goes low and stays low when VCC drops below VRST (reset threshold selected by the customer), or when MR is logic low. It remains low for trec (200ms, typical) AFTER VCC rises above VRST and MR goes from low to high. 2.1.6 MR, manual reset input A logic low on MR asserts the RST output. The RST output remains asserted as long as MR is low and for trec after MR returns to high. This active low input has an internal 40 k (typical) pull-up resistor. It can be driven from a TTL or CMOS logic line or shorted to ground with a switch. Leave it open if unused. 2.1.7 PFO, power-fail output (open drain) When PFI is less than VPFI (power-fail input threshold voltage) or VCC falls below VSW (battery switchover threshold ~ 2.4 V), PFO goes low, otherwise, PFO remains high. Leave this pin open if unused. 2.1.8 PFI, power-fail input When PFI is less than VPFI, or when VCC falls below VSW (see PFO, above), PFO goes active-low. If this function is unused, connect this pin to VSS. 2.1.9 VREF, reference voltage output (1.237, typ) This is valid only when VCC is between 2.4 V and 3.6 V. When VCC falls below 2.4 V (VSW), VREF is pulled to ground with an internal 100 k resistor. This is an optional feature available on the STM1403A. On the STM1403B/C, this pin is VTPU (internally switched VCC or VBAT). If unused, this pin should float. 12/35 STM1403 Pin descriptions 2.1.10 VOUT This is the supply voltage output. When VCC rises above VSO (battery backup switchover voltage), VOUT is supplied from VCC. In this condition, VOUT may be connected externally to VCC through a p-channel MOSFET switch. When VCC falls below the lower value of VSW (~2.4 V), or VBAT, VOUT is supplied from VBAT. It is recommended that the VOUT pin be connected externally to a capacitor that will retain a charge for a period of time, in case an intruder forces VCC or VBAT to ground. The rectifying diode connected from the positive terminal of the battery to the VBAT pin of the STM1403 will prevent discharge of the capacitor. Three variations of parts will be offered with the following options: 1. 2. 3. STM1403A: VOUT remains ON when SAL is active-low; Vccsw pin will continue to operate in normal mode (see Section 2.1.3: Vccsw, VCC switch output on page 11); STM1403B: VOUT is taken to High-Z when SAL is active-low; Vccsw pin will be set to high when this occurs; and STM1403C: VOUT is driven to ground when SAL is active-low; Vccsw pin will be set to high when this occurs. 2.1.11 VTPU For STM1403B and STM1403C, this pin provides pull-up voltage for the physical tamper pins (TP1-4). This pin is not to be used as voltage supply source for any other purpose. Note: VTPU is the internally switched supply voltage from either the VCC pin or the VBAT pin. 2.1.12 VCC This is the supply voltage (2.2 V to 3.6 V). 2.1.13 VBAT This is the secondary (backup battery) supply voltage. The pin is connected to the positive terminal of the battery with a rectifying diode like the BAT54J from STMicroelectronics for reverse charge protection. Voltage at this pin, after diode rectification, will be approximately 0.2 V less than the battery voltage, and will depend on the type of battery used as well as the IBAT being drawn. (A capacitor of at least 1.0 F connected between the VBAT pin and VSS is required.) If no battery is used, connect the VBAT pin to the VCC pin. 2.1.14 VSS Ground, VSS, is the reference for the power supply. It must be connected to system ground. 13/35 Operation STM1403 3 3.1 Operation Reset input The STM1403 security supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), or when the push-button reset input (MR) is taken low. RST is guaranteed to be a logic low for 0V < VCC < VRST if VBAT is greater than 1V. Without a backup battery, RST is guaranteed valid down to VCC =1V. During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, trec. After this interval RST returns high. If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. 3.2 Push-button reset input A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 25 on page 24) after it returns high. The MR input has an internal 40 k pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to ground to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 F capacitor from MR to VSS to provide additional noise immunity. MR may float, or be tied to VCC when not used. 3.3 Backup battery switchover In the event of a power failure, it may be necessary to preserve the contents of external SRAM through VOUT. With a backup battery installed with voltage VBAT, the devices automatically switch the SRAM to the backup supply when VCC falls. Note: If backup battery is not used, connect both VBAT and VOUT to VCC. This family of security supervisors does not always connect VBAT to VOUT when VBAT is greater than VCC. VBAT connects to VOUT (through a 100 switch) when VCC is below VSW (~2.4 V) or VBAT (whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V battery) to have a higher voltage than VCC. Assuming that VBAT > 2.0 V, switchover at VSO ensures that battery backup mode is entered before VOUT gets too close to the 2.0 V minimum required to reliably retain data in most external SRAMs. When VCC recovers, hysteresis is used to avoid oscillation around the VSO point. VOUT is connected to VCC through a 3 PMOS power switch. Note: The backup battery may be removed while VCC is valid, assuming VBAT is adequately decoupled (0.1 F typ), without danger of triggering a reset. 14/35 STM1403 Table 3. Pin VOUT VCC PFI PFO MR RST VBAT Vccsw VREF BLD VTPU Operation I/O status in battery backup Status Connected to VBAT through internal switch Disconnected from VOUT Disabled Logic low Disabled Logic low Connected to VOUT Logic high Pulled to VSS below 2.4 V (VSW) Logic high Connected to VBAT through an internal switch 3.4 Power-fail input/output The power-fail input (PFI) is compared to an internal reference voltage (independent from the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the power-fail output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 4 on page 9) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the STM1403 or the microprocessor drops below the minimum operating voltage. During battery backup, the power-fail comparator is turned off and PFO goes (or remains) low (see Figure 9 on page 16). This occurs after VCC drops below VSW (~2.4V). When power returns, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. PFO may be connected to MR so that a low voltage on PFI will generate a reset output. 3.5 Applications information These supervisor circuits are not short-circuit protected. Shorting VOUT to ground excluding power-up transients such as charging a decoupling capacitor - destroys the device. Decouple both VCC and VBAT pins to ground by placing 0.1 F capacitors as close to the device as possible. 15/35 Operation Figure 9. Power-fail comparator waveform VCC VRST STM1403 VSW (2.4V) trec PFO PFO follows PFI PFO follows PFI RST AI08861a 3.6 Negative-going VCC transients and undershoot The STM1403 devices are relatively immune to negative-going VCC transients (glitches). Figure 23 on page 22 was generated using a negative pulse applied to VCC, starting at VRST + 0.3 V and ending below the reset threshold by the magnitude indicated (comparator overdrive). The graph indicates the maximum pulse width a negative VCC transient can have without causing a reset pulse. As the magnitude of the transient increases (further below the threshold), the maximum allowable pulse width decreases. Any combination of duration and overdrive which lies under the curve will NOT generate a reset signal. Typically, a VCC transient that goes 100 mV below the reset threshold and lasts 40 s or less will not cause a reset pulse. A 0.1 F bypass capacitor mounted as close as possible to the VCC pin provides additional transient immunity (see Figure 10). In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 10. Supply voltage protection VCC VCC 0.1F DEVICE VSS AI02169 16/35 STM1403 Tamper detection 4 4.1 Tamper detection Physical There are four (4) high-impedance physical tamper detect input pins, 2 normally set to high (NH) and 2 normally set to low (NL). Each input is designed with a glitch immunity (see Table 7 on page 28). These inputs can be connected externally to several types of actuator devices (e.g., switches, wire mesh). A tamper on any one of the four inputs that causes its state to change will trigger the security alarm (SAL) and drive it to active-low. Once the tamper condition no longer exists, the SAL will return to its normal high state. TP1 and TP3 are set normally to high (NH). They are connected externally through a closed switch or a high-impedance resistor to VOUT (in the case of STM1403A) or VTPU (in the case of STM1403B/C), A tamper condition will be detected when the input pin is pulled low (see Figure 5 and Figure 6). If not used, tie the pin to VOUT or VTPU. TP2 and TP4 are set normally to low (NL). They are connected externally through a highimpedance resistor or a closed switch to VSS. A tamper condition will be detected when the input pin is pulled high (see Figure 7 and Figure 8). If not used, tie the pin to VSS. 4.2 Supply voltage The internally switched supply voltage, VINT (either VCC input or VBAT input) is continuously monitored. If VINT should exceed the over voltage trip point, VHV (set at 4.2V, typical), or should go below the under voltage trip point, VLV (set at 2.0 V, typical). SAL will be driven active-low. Once the tamper condition no longer exists, the SAL pin will return to its normal high state. When no tamper condition exists, SAL is normally high (see Section 2: Pin descriptions on page 11). When a tamper is detected, the SAL is activated (driven low), independent of the part type. VOUT can be driven to one of three states, depending on which variant of STM1403 is being used (see Table 1: Device summary on page 1): ON High-Z or Ground (VSS) Note: The STM1403 must be initially powered above VRST to enable the tamper detection alarms. For example, if the battery is on while VCC = 0V, no alarm condition can be detected until VCC rises above VRST (and trec expires). From this point on, alarms can be detected either on battery or VCC. This is done to avoid false alarms when the device goes from no power to its operational state. 17/35 Typical operating characteristics STM1403 5 Note: Typical operating characteristics Typical values are at TA = 25C. Figure 11. VBAT -to-VOUT on-resistance vs. temperature VBAT - to - VOUT ON-RESISTANCE [] 220 VCC = 0V 200 180 160 140 120 100 -60 VBAT = 2V VBAT = 3V VBAT = 3.3V -40 -20 0 20 40 60 80 100 120 140 AI09691 TEMPERATURE [C] Figure 12. Supply current vs. temperature (no load) 30 25 Supply Current [A] 20 2.5V 15 3.3V 3.6V 10 5 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 AI09692 TEMPERATURE [C] 18/35 STM1403 Figure 13. VPFI threshold vs. temperature 1.255 1.250 1.245 1.240 1.235 Typical operating characteristics VPFI THRESHOLD [V] VCC = 3.3V VCC = 2.5V 1.230 VBAT = 3.0V 1.225 -50 -30 -10 10 30 50 70 90 110 130 AI09693 TEMPERATURE [C] Figure 14. Reset comparator propagation delay vs. temperature PROPAGATION DELAY [s] 24 22 20 18 16 14 12 10 -60 -40 -20 0 20 40 60 80 100 AI09143 VBAT = 3.0V 100mV OVERDRIVE TEMPERATURE [C] Figure 15. Power-up trec vs. temperature 215 210 trec [ms] 205 200 195 -50 -30 -10 10 30 50 70 90 110 130 AI09144 TEMPERATURE [C] 19/35 Typical operating characteristics Figure 16. Normalized reset threshold vs. temperature NORMALIZED RESET THRESHOLD [V] 1.002 STM1403 1.000 0.998 0.996 VBAT = 3.0V 0.994 -60 -40 -20 0 20 40 60 80 100 120 140 AI09145 TEMPERATURE [C] Figure 17. PFI to PFO propagation delay vs. temperature 9 8 PROPAGATION DELAY [s] 7 6 5 4 3 2 1 0 -60 -40 -20 0 20 40 60 80 100 120 140 AI09148 TEMPERATURE [C] Figure 18. RST output voltage vs. supply voltage 3.5 3.0 RST OUTPUT VOLTAGE [V] 2.5 2.0 VCC VRST 1.5 1.0 0.5 0 500 ms/div AI09149b 20/35 STM1403 Figure 19. RST response time (assertion) 4.0 Typical operating characteristics 3.0 VCC VCC LEVEL [V] 2.0 VRST 1.0 0.0 2 s/div AI09151b Figure 20. Power-fail comparator response time (assertion) 4.0 1.45 1.40 3.0 VPFO LEVEL [V] 1.35 PFO 2.0 1.30 PFI 1.25 1.0 1.20 0.0 2s/div 1.15 AI09153b Figure 21. Power-fail comparator response time (de-assertion) 4.0 3.5 1.40 3.0 1.45 VPFO LEVEL (V) 2.5 PFO 2.0 1.5 1.0 1.20 0.5 0.0 2 s/div 1.15 AI09154 1.30 PFI 1.25 VPFI LEVEL (V) 1.35 VPFI LEVEL [V] 21/35 Typical operating characteristics Figure 22. VCC to reset propagation delay vs. temperature 60 STM1403 PROPAGATION DELAY [s] 50 40 10V/ms 30 20 10 0 -60 -40 -20 0 20 40 60 80 100 1V/ms 0.25V/ms TEMPERATURE [C] AI09155 Figure 23. Maximum transient duration vs. reset threshold overdrive 250 TRANSIENT DURATION [s] 200 150 100 50 0 1 10 100 1000 10000 AI09156 RESET COMPARATOR OVERDRIVE, VRST - VCC [mV] 22/35 STM1403 Maximum ratings 6 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Symbol TSTG TSLD(1) VIO VCC/VBAT IO PD Absolute maximum ratings Parameter Storage temperature (VCC off, VBAT off) Lead solder temperature for 10 seconds Input or output voltage Supply voltage Output current Power dissipation Value -55 to 150 260 -0.3 to VCC +0.3 -0.3 to 4.5 20 320 Unit C C V V mA mW Note: Reflow at peak temperature of 255C to 260C for < 30 seconds (total thermal budget not to exceed 180C for between 90 to 150 seconds). 23/35 DC and AC parameters STM1403 7 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 5: Operating and AC measurement condition. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC measurement condition Parameter VCC/VBAT supply voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing ref. voltages STM1403 2.2 to 3.6 -40 to 85 5 0.2 to 0.8VCC 0.3 to 0.7VCC Unit V C ns V V Figure 24. AC testing input/output waveforms 0.8VCC 0.7VCC 0.3VCC AI02568 0.2VCC Figure 25. MR timing waveform MR tMLRL RST tMLMH trec AI09694 Figure 26. STM1403 switchover diagram, condition A (VBAT < VSW) VCC = 3.3V VRST VSW = 2.4V VBAT VBAT - 75mV VOUT VBAT - 35mV AI10463 Figure 27. STM1403 switchover diagram, condition B (VBAT > VSW) VCC = 3.3V VBAT VSW = 2.4V VSW + 40mV AI10464 VOUT 24/35 STM1403 Table 6. Sym VCC, VBAT(2) DC and AC parameters DC and AC characteristics Alternative Description Test condition(1) Min Typ Max Unit Operating voltage VCC supply current (STM1403A) TA = -40 to +85C 2.2 45 3.6 60 45 V A A Typ @ 3.3 V, 25C ICC VCC supply current (STM1403B,C) VCC supply current in battery backup mode IBAT(3) VBAT supply current in battery backup mode Excluding IOUT (VBAT = 2.3 V, VCC = 2.0 V, MR = VCC) Excluding IOUT (VBAT = 3.6 V) IOUT1 = 5 mA(4) (VCC > VSW) VOUT1 VOUT voltage (active) IOUT1 = 80 mA (VCC > VSW) IOUT1 = 250 A, VCC > VSW(4) VOUT voltage (battery backup) IOUT2 = 250 A, VBAT = 2.2 V IOUT2 = 1 mA, VBAT = 2.2 V ISOURCE = 500 A (VCC > VSW) ISOURCE = 100 A (VBAT = 2.2 V) MR = 0 V; VCC = 3 V 0 V = VIN = VCC 0 V = VIN = VCC 0 V = VIN = VCC(5) VRST (max) < VCC < 3.6V VCC = VRST (max), ISINK = 3.2mA IOL = 40A; VCC = 1.0V; VBAT = VCC; TA = 0C to 85C IOL = 200A; VCC = 1.2V; VBAT = VCC 20 -25 -1 -1 0.7VCC 0.3VCC 0.3 VCC - 0.3 VBAT - 0.10 75 2 350 +25 +1 +1 VCC - 0.03 VCC - 0.3 VCC - 0.0015 VBAT - 0.1 30 25 35 A 2.8 VCC - 0.015 VCC - 0.15 VCC - 0.0006 VBAT - 0.04 VBAT - 0.16 4.0 A V V V V V V V A nA A A V V V VOUT2 VTPU1 VTPU2 Internal switched supply voltage (active) Internal switched supply voltage (battery backup) Input leakage current (MR) ILI Input leakage current (PFI) Input leakage current (TP1-TP4) ILO VIH VIL VOL Output leakage current Input high voltage (MR) Input low voltage (MR) Output low voltage (PFO, RST, Vccsw, SAL, BLD) 0.3 V VOL Output low voltage (RST) 0.3 V 25/35 DC and AC parameters Table 6. Sym VOHB STM1403 DC and AC characteristics (continued) Alternative Description VOH battery backup (Vccsw) Pull-up supply voltage (open drain) Test condition(1) ISOURCE = 100 A, RST, SAL, BLD, PFO Min 0.8VBAT 3.6 Typ Max Unit V V Power-fail comparator VPFI PFI input threshold PFI hysteresis tPFD PFI to PFO propagation delay PFI falling (VCC < 3.6 V) PFI Rising (VCC < 3.6 V) 1.212 1.237 10 2 1.262 20 V mV s Battery switchover Powerdown Power-up VSW Hysteresis Battery low voltage detect On power-up only M N O 2.25 2.45 3.14 2.30 2.50 3.20 2.34 2.55 3.26 V V V VBAT > VSW VBAT < VSW VBAT > VSW VBAT < VSW VSW VBAT VSW VBAT 2.4 40 V V V V V mV Battery backup switchover voltage (6)(7) VSO VDET Battery detect threshold Voltage reference (option for STM1403A)(8) Voltage reference (see Section 2.1.9: VREF, reference voltage output (1.237, typ) on page 12) Source current -40 to 0C Sink current Output voltage noise f = 100 Hz to 100 kH 10 10 15 13 10-100 A A Vrms 0C to 85C -40 to 0C 0C to 85C IREF+ IREF- Vn 1.212 1.200 15 1.237 1.237 25 1.262 1.274 V V A VREF 26/35 STM1403 Table 6. Sym DC and AC parameters DC and AC characteristics (continued) Alternative Description Test condition(1) Min Typ Max Unit Reset thresholds T VCC falling VCC rising VRST(9) Reset threshold S VCC falling VCC rising R trec RST pulse width VCC falling VCC rising 3.00 3.00 2.85 2.85 2.55 2.55 140 3.075 3.085 2.925 2.935 2.625 2.635 200 3.15 3.17 3.00 3.02 2.70 2.72 280 V V V V V V ms Push-button reset input tMLMH tMLRL tMR tMRD MR pulse width MR to RST output delay 100 60 500 ns ns 1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = VRST (max) to 3.6 V; and VBAT = 2.8 V (except where noted); typical values are for 3.3 V and 25C. 2. VCC supply current, logic input leakage, push-button reset functionality, PFI functionality, state of RST tested at VBAT = 3.6 V, and VCC = 3.6 V. The state of RST and PFO is tested at VCC = VCC (min). VBAT is voltage measured at the pin. 3. Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V. 4. Guaranteed by design. 5. The leakage current measured on the RST, SAL, PFO, and BLD pins are tested with the output not asserted (output high impedance). 6. When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW. 7. When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) - 75 mV. 8. Maximum external capacitive load on VREF pin cannot exceed 1nF. 9. The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10 mV (typ) hysteresis, which prevents internal oscillation. 27/35 DC and AC parameters Table 7. Sym VHV VLV STM1403 Physical and environmental tamper detection levels Parameter Test conditions(1) Min 4.0 1.9 VHV + 200 mV or VLV - 200 mV VOUT - 1.3 V(2) 0.3 VHTP = VOUT/VTPU; VLTP = VSS VDD = 3.6 Typ 4.2 2.0 25 Max 4.4 2.1 50 VOUT - 0.3 V(2) 1.0 Unit V V s Overvoltage trip level Undervoltage trip level SAL propagation delay time (after over/under voltage detection) VHTP VLTP Trip point for NH physical tamper input pins (TP1 or TP3) Trip point for NL physical tamper input pins (TP2 or TP4) SAL propagation delay time(3) (after physical tamper pin detection) Physical tamper input (TPX) glitch immunity V V 30 50 s 15 s 1. Valid for ambient operating temperature: TA = -40 to 85C; VCC = VLV to VHV (except where noted). 2. In the case of STM1403A, physical tamper input pins (TPX) are referenced to VOUT (pin 12). In the case of STM1403B or C, TPX are referenced to VTPU pin (pin 9). 3. VCC = VRST (max) to 3.6 V 28/35 STM1403 Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 28. QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline D E A3 A1 A ddd C b L e K 1 2 E2 3 Ch K D2 QFN16-A Note: Drawing is not to scale. 29/35 Package mechanical data Table 8. QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mechanical data mm Symb Typ A A1 A3 b D D2 E E2 e K L ddd Ch N 0.90 0.02 0.20 0.25 3.00 1.70 3.00 1.70 0.50 0.20 0.40 - - Min 0.80 0.00 - 0.18 2.90 1.55 2.90 1.55 - - 0.30 0.08 0.33 16 Max 1.00 0.05 - 0.30 3.10 1.80 3.10 1.80 - - 0.50 - - Typ 0.035 0.001 0.008 0.010 0.118 0.067 0.118 0.067 0.020 0.008 0.016 - - Min 0.032 0.000 - 0.007 0.114 0.061 0.114 0.061 - - 0.012 0.003 0.013 16 inches STM1403 Max 0.039 0.002 - 0.012 0.122 0.071 0.122 0.071 - - 0.020 - - Figure 29. QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint 1.60 3.55 2.0 AI09126 0.28 Note: Substrate pad should be tied to VSS. 30/35 STM1403 Part numbering 9 Table 9. Example: Part numbering Ordering information scheme (see Figure 30 on page 32 for marking information) STM1403 A T M Q 6 F Device type STM1403: physical, voltage tamper detect VOUT status (SAL = active-low) A: VOUT = ON; Vccsw = normal mode B(1): VOUT = High-Z; Vccsw = high C: VOUT = ground; Vccsw = high Reset threshold voltage T: VRST = 3.00 V to 3.15 V S: VRST = 2.85 V to 3.00 V R: VRST = 2.55 V to 2.70 V Battery low voltage detect threshold (VDET) M: VDET = 2.3 V (typ) N: VDET = 2.5 V (typ) O: VDET = 3.2 V (typ) Package Q = QFN16 (3 mm x 3 mm) Temperature range 6 = -40 to 85C Shipping method F = ECOPACK(R) package, tape & reel 1. Contact local ST sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. 31/35 Part numbering Figure 30. Topside marking information 03 XXX(1) YWW(2) STM1403 AI11878 1. Options codes: X = A, B, or C (for VOUT) X = T, S, or R (for reset threshold) X = M, N, or O (for battery low voltage detect threshold) 2. Traceability codes Y = Year WW = Work Week 32/35 STM1403 Revision history 10 Revision history Table 10. Date 11-Oct-2004 26-Nov-2004 22-Dec-2004 03-Feb-2005 25-Feb-2005 06-May-2005 05-Aug-2005 18-Oct-2005 07-Feb-2007 20-Aug-2008 Document revision history Revision 1 1.1 1.2 1.3 1.4 1.5 2 3 4 5 First edition Corrected footprint dimensions; update characteristics (Figure 1, 2, 3, 4, 5, 6, 7, 8, 26, 27, 29; Table 1, 2, 3, 6, 7) Update characteristics ( Figure 4; Table 6, 7, 9) Update characteristics (Figure 4; Table 6, 7) Update temperature trip limits (Table 9) Update characteristics (Figure 3, 4, 28; Table 6, 7) Removed STM1404 references (Figure 1, 2, 3, 4, 5, 6, 7, 8, 26, 27; Table 1, 2, 5, 6, 7, 9) Update hardware hookup, characteristics, Lead-free text; add marking information (Figure 4, 30; Table 6, 7, 9) Update cover page, Table 7, and part numbering (Table 9). Minor formatting changes, updated Table 1 and 7. Changes 33/35 STM1403 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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